Various improvements have been made to variable length coding methods and variable length decoding methods used for moving images in consideration of uses of these methods, and so on. As international standard coding methods, for example, H.261, H.263, MPEG1, MPEG 2, MPEG4, and so on are provided.
A conventional variable length coding and decoding apparatus stores table data corresponding to various coding methods in a table memory (table data include a variable length coding code corresponding to combination data about a combination of the number of zero runs and a level value and the code length of the variable length coding code, and are stored at an address corresponding to the combination data) so as to support various types of variable length coding/decoding including international standard methods without persisting in using its own variable length coding/decoding.
Furthermore, a variable length coding and decoding apparatus which has a variable length coding unit and a variable length decoding unit having different circuit structures, and which has a variable length coding function and a variable length decoding function converts input data into an address in a table memory when extracting desired table data from the table memory (refer to patent reference 1).
Although a conventional variable length coding and decoding apparatus can support various variable length coding/decoding methods including international standard methods, the conventional variable length coding and decoding apparatus has to include a coding circuit and a decoding circuit separately because the circuit structure used for variable length coding and that used for variable length decoding differ from each other.
Furthermore, because a table for storing a variable length coding code and the code length of the variable length coding code is implemented in a memory, it is necessary to make the bit width of the memory match the longest variable length coding code, and therefore a useless memory area is produced for a variable length coding code having a shorter code length.
In addition to the above-mentioned variable length coding and decoding apparatus, a variable length coding and decoding apparatus which eliminates the necessity of disposing a coding circuit and a decoding circuit separately to prevent occurrence of any useless memory area has been developed (for example, refer to patent reference 2).
More specifically, the variable length coding and decoding apparatus disclosed in patent reference 2 is comprised of components as mentioned below and its components which are not commonly used at the time of coding and at the time of decoding are limited to only an unpack unit and a pack unit, thereby eliminating the necessity of disposing a coding circuit and a decoding circuit separately.                A variable length coding/decoding table unit which can be dynamically restructured        The unpack unit which furnishes a bit stream to the table unit at the time of decoding        The pack unit which carries out packing of a bit stream, which is outputted from the table unit at the time of coding, in such a way that the bit stream has a memory width        A bit stream memory which stores a coded result or a bit stream to be decoded        A coefficient memory which stores a decoded result or a coefficient to be coded        A control register which stores control information outputted from a CPU        A bus I/F which performs I/F with the CPU        
Furthermore, in this variable length coding and decoding apparatus, the variable length coding/decoding table unit is constructed using cell elements which can be restructured dynamically in order to eliminate the existence of any useless memory area, and table data divided finely are assigned to the cell elements which can be restructured dynamically with the variable length coding/decoding table unit being assumed as a search tree.
The cell elements which can be restructured dynamically are comprised of elements for connection which implement a branched architecture of the search tree, and functional elements which implement nodes of the search tree.
Register groups in which configuration data for implementing the search tree are written (a connection information register group, a bit selection register group, a comparison object register group, and an output value register group) exist in each cell.    [Patent reference 1] JP,2001-308715,A (paragraph numbers [0023] to [0028], and FIG. 1)    [Patent reference 2] JP,2006-101171,A (paragraph numbers [0010] to [0013], and FIG. 1)
A problem with conventional variable length coding and decoding apparatuses which are constructed as mentioned above is that when performing variable length coding or variable length decoding, they have to carry out a process of writing configuration data for implementing a search tree in register groups of each cell (a connection information register group, a bit selection register group, a comparison object register group, and an output value register group), and it is therefore difficult to achieve an improvement in the speed of the variable length coding and in the speed of the variable length decoding.
The present invention is made in order to solve the above-mentioned problems, and it is therefore an object of the present invention to provide a table device which can eliminate the need for performing a process of writing configuration data in a register group of each cell, thereby being able to achieve an improvement in the speed of a variable length coding process and in the speed of a variable length decoding process.
It is another object of the present invention to provide a variable length coding apparatus which implements a table device which can achieve an improvement in the speed of a variable length coding process and in the speed of a variable length decoding process therein, a variable length decoding apparatus which implements the table device therein, and a variable length coding and decoding apparatus which implements the table device therein.